View MT4LSDT232UDG-8XX_7717381.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

09005aef80948ad4 micron technology, inc., reserves the right to change products or specifications without notice. sd2_4c1_2x32udg_a.fm - rev. a 2/03 en 1 ?2003, micron technology inc. 4mb, 8mb (x32) sdram dimms synchronous dram module mt2lsdt132u - 4mb mt4lsdt232ud - 8mb for the latest data sheet, please refer to the micron web site: www.micron.com/moduleds features ? jedec pinout in a 100-pin, dual in-line memory module (dimm) 4mb (1 meg x32) and 8mb (2 meg x32) utilizes 100 mhz and 125 mhz sdram components single +3.3v power supply fully synchronous; all signals registered on positive edge of system clock internal sdram device pipelined operation, compatible with 2 n prefetch architecture, allows column address changes every clock cycle internal sdram device banks for hiding row access/precharge programmable burst length s: 1, 2, 4, 8, or full page auto precharge and auto refresh modes 64ms, 2,048-cycle refresh (31.25s refresh interval for power saving); or 64ms, 2,048-cycle refresh (15.625s refresh interval) lvttl-compatible inputs and outputs serial presence-detect (spd ) figure 1: 100-pin dimm (mo?161) table 1: timing parameters cl = cas (read) latency module marking clock frequency access time setup time hold time cl = 2 cl = 3 -8 125 mhz ? 6ns 2ns 1ns -10 100 mhz 10ns ? 2ns 1ns options marking package 100-pin dimm (gold) g 100-pin dimm (lead-free) y frequency / cas latency 125 mhz (8ns) / cl = 3 -8 100 mhz (10ns) / cl = 2 -10 table 2: part numbers part number configuration system bus speed mt2lsdt132ug-8_ 1 meg x32 125 mhz mt2lsdt132uy-8_ 1 meg x32 125 mhz mt2lsdt132ug-10_ 1 meg x32 100 mhz mt2lsdt132uy-10_ 1 meg x32 100 mhz mt4lsdt232udg-8_ 2 meg x32 125 mhz mt4lsdt232udy-8_ 2 meg x32 125 mhz mt4lsdt232udg-10_ 2 meg x32 100 mhz mt4lsdt232udy-10_ 2 meg x32 100 mhz table 3: address table module density 4mb 8mb refresh count 2k or 4k 2k or 4k device banks 2 (ba0) 2 (ba0) device configuration 1 meg x 16 1 meg x 16 device row addressing 2k (a0 - a10) 2k (a0 - a10) device column addressing 256 (a0 - a7) 256 (a0 - a7) module ranks 1 (s0#, s2#) 2 (s0#, s2#; s1#, s3#)
4mb, 8mb (x32) sdram dimms 09005aef80948ad4 micron technology, inc., reserves the right to change products or specifications without notice. sd2_4c1_2x32udg_a.fm - rev. a 2/03 en 2 ?2003, micron technology inc. figure 2: pin locations (100-pin dimm) table 4: pin assignment front (100-pin dimm) pin symbol pin symbol pin symbol pin symbol 1vss 13 a0 26 vss 38 dq16 2dq0 14 a2 27 cke0 39 dq17 3dq1 15 a4 28 we# 40 dq18 4dq2 16 a6 29 s0# 41 dq19 5dq3 17 a8 30 s2# 42 v dd 6v dd 18 a10 31 v dd 43 dq20 7dq4 19 nc 32 nc 44 dq21 8dq5 20 nc 33 nc 45 dq22 9dq6 21 v dd 34 nc 46 dq23 10 dq7 22 nc 35 nc 47 vss 11 dqmb0 23 rfu 36 vss 48 sda 12 vss 24 rfu 37 dqmb2 49 scl 25 ck0 50 v dd table 5: pin assignment back (100-pin dimm) pin symbol pin symbol pin symbol pin symbol 51 vss 63 a1 76 vss 88 dq24 52 dq8 64 a3 77 cke1 89 dq25 53 dq9 65 a5 78 nc 90 dq26 54 dq10 66 a7 79 s1# 91 dq27 55 dq11 67 a9 80 s3# 92 v dd 56 v dd 68 ba0 81 v dd 93 dq28 57 dq12 69 nc 82 nc 94 dq29 58 dq13 70 nc 83 nc 95 dq30 59 dq14 71 v dd 84 nc 96 dq31 60 dq15 72 ras# 85 nc 97 vss 61 dqmb1 73 cas# 86 vss 98 sa0 62 vss 74 rfu 87 dqmb3 99 sa1 75 ck1 100 sa2 pin 50 pin 23 pin 1 pin100 pin 51 pin 73 front view back view indicates a v dd pin indicates a v ss pin (not populated for the 4mb module) u1 u2 u3 u4 u5
4mb, 8mb (x32) sdram dimms 09005aef80948ad4 micron technology, inc., reserves the right to change products or specifications without notice. sd2_4c1_2x32udg_a.fm - rev. a 2/03 en 3 ?2003, micron technology inc. table 6: pin descriptions pin numbers may not correlate with symbols. refer to the pin assignment tables on page 2 for more information. pin number symbol type description 28, 72, 73 we#, ras#, cas# input command inputs: ras#, cas# and we# (along with s#) define the command being entered. 25, 75 ck0, ck1 input clock: ck is driven by the system clock. all sdram input signals are sampled on the positive edge sdram input signals are sampled on the positive edge of ck. ck also increments the internal burst counter and controls the output registers. 27, 77 cke0, cke1 input clock enable: cke activates (high) and deactivates (low) the ck signal. deactivating the clock provides power-down and self refresh operation (all banks idle), or clock suspend operation (burst access in progress). cke is synchronous except after the device enters power-down and self refresh modes, where cke becomes asynchronous until after exiting the same mode. the input buffers, including ck, are disabled during power-down and self refresh modes, providing low standby power. 29, 30, 79, 80 s0#-s3# input chip select: s# enables (registered low) or disables (registered high) the the command decoder. all commands are masked when s# is registered high. s# is considered part of the command code. 11, 37, 61, 87 dqmb0- dqmb3 input input/output mask: dqmb is an input mask signal for write accesses and an output enable signal for read accesses. input data is masked when dqmb is sampled high during a write cycle. the output buffers are placed in a high- z state (after a two-clock latency) when dqmb is sampled high during a read cycle. 68 ba0 input bank address: ba0 defines to which bank the active, read, write or precharge command is being applied. 13, 14, 15, 16, 17, 18, 63, 64, 65, 66, 67 a0-a10 input address inputs: provide the row address for active commands, and the column address and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective device bank. a10 is sampled during a precharge co mmand to determines whether the precharge applies to one device bank (a10 low, device bank selected by ba0) or all device banks (a10 high). the address inputs also provide the op- code during a load mode register command. 49 scl input serial clock for presence-detect: scl is used to synchronize the presence- detect data transfer to and from the module. 98-100 sa0-sa2 input presence-detect address inputs: thes e pins are used to configure the presence-detect device. 2-5, 7-10, 38-41, 43-46, 52-55, 57- 60, 88-91, 93-96 dq0-dq31 input/ output data i/os: data bus. 48 sda input/ output serial presence-detect data: sda is a bidirectional pin used to transfer addresses and data into and data out of the presence-detect portion of the module. 6, 21, 31, 42, 50, 56, 71, 81, 92 v dd supply power supply: +3.3v 0.3v. 1, 12, 26, 36, 47, 51, 62, 76, 86, 97 v ss supply ground. 23, 24, 74 rfu ? reserved for future use: these pins should be left unconnected. 19, 20, 22, 32-35, 69, 70, 78, 82-85 nc ? not connected.
4mb, 8mb (x32) sdram dimms 09005aef80948ad4 micron technology, inc., reserves the right to change products or specifications without notice. sd2_4c1_2x32udg_a.fm - rev. a 2/03 en 4 ?2003, micron technology inc. figure 3: functional block diagram ( mt2lsdt132u) a0 spd scl sda a1 a2 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqmh u1 dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqmb0 s0# ras# cas# cke0 we# ras#: sdrams cas#: sdrams cke: sdrams we#: sdrams a0-a10: sdrams ba0: sdrams a0-a10 ba0 v dd v ss sdrams sdrams ck0 u1 u2 6.8pf 10pf dq dq dq dq dq dq dq dq dqml cs# dqmb1 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dqmh u2 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dqmb2 s2# dqml cs# dqmb3 ck1 sa0 sa1 sa2 wp dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq u5 note: 1. all resistor values are 22 unless otherwise specified. 2. per industry standard, micron utilizes various component speed grades as refer- enced in the module part numbering guide at www.micron.com/numberguide . sdrams = mt48lc1m16a1tg
4mb, 8mb (x32) sdram dimms 09005aef80948ad4 micron technology, inc., reserves the right to change products or specifications without notice. sd2_4c1_2x32udg_a.fm - rev. a 2/03 en 5 ?2003, micron technology inc. figure 4: functional bl ock diagram (mt4lsdt232ud) a0 spd scl sda a1 a2 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqmh u1 dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqmb0 s0# ras# cas# cke0 cke1 we# ras#: sdrams cas#: sdrams cke: sdrams u1-u2 cke: sdrams u3-u4 we#: sdrams a0-a10: sdrams ba0: sdrams a0-a10 ba0 v dd v ss sdrams sdrams ck0 u1 u2 6.8pf 6.8pf dq dq dq dq dq dq dq dq dqml cs# dqmb1 dqmh u3 dqml cs# s1# dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dqmh u2 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dqmb2 s2# dqml cs# dqmb3 dqmh u4 dqml cs# s3# ck1 u3 u4 sa0 sa1 sa2 wp dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq u5 sdrams = mt48lc1m16a1tg note: 1. all resistor values are 22 unless otherwise specified. 2. per industry standard, micron utilizes various component speed grades as referenced in the module part numbering guide at www.micron.com/ numberguide .
4mb, 8mb (x32) sdram dimms 09005aef80948ad4 micron technology, inc., reserves the right to change products or specifications without notice. sd2_4c1_2x32udg_a.fm - rev. a 2/03 en 6 ?2003, micron technology inc. general description the micron mt2lsdt132u and mt4lsdt232ud are high-speed cmos, dynamic random-access, 4mb and 8mb memory modules organized in a x32 configu- ration. these modules use sdram devices which are internally configured as dual-bank drams with a syn- chronous interface (all signals are registered on the positive edge of the clock signal ck). read and write accesses to these sdram modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then fol- lowed by a read or write command. the address bits registered coincident with the active command are used to select the device bank and row to be accessed (ba0 selects the device bank, a0?a10 for device row). the address bits registered coincident with the read or write command (ba0, a0?a7) are used to select the starting device bank and column location for the burst access. these modules provide for programmable read or write burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. these modules use an internal pipelined architecture to achieve high-speed operation. this architecture is compatible with the 2 n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high- speed, fully random access. precharging one device bank while accessing the other device bank will hide the precharge cycles and provide seamless, high- speed, random access operation. these modules are designed to operate in 3.3v, low- power memory systems. an auto refresh mode is pro- vided, along with a power-saving, power-down mode. all inputs, outputs, and clocks are lvttl-compatible. sdram modules offer substantial advances in dram operating performance, including the ability to synchronously burst data at a high data rate with auto- matic column-address generation, the ability to inter- leave between internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. for more information regarding sdram opera- tion, refer to the 16mb sdram component data sheet. serial presence-detect operation these modules incorporate serial presence-detect (spd). the spd function is implemented using a 2,048-bit eeprom. this nonvolatile storage device contains 256 bytes. the first 128 bytes can be pro- grammed by micron to identify the module type and various sdram organizations and timing parameters. the remaining 128 bytes of storage are available for use by the customer. system read/write operations between the master (system logic) and the slave eeprom device (dimm) occur via a standard i 2 c bus using the dimm?s scl (clock) and sda (data) signals. write protect (wp) is tied to ground on the module, permanently disabling hardware write protect. initialization sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined opera- tion. once power is applied to v dd and v dd q (simulta- neously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the sdram requires a 100s delay prior to issuing any command other than a com- mand inhibit or nop. starting at some point during this 100s period and continuing at least through the end of this period, command inhibit or nop com- mands should be applied. once the 100s delay has been satisfied with at least one command inhibit or nop command having been applied, a precharge command should be applied. all device banks must then be precharged, thereby placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed. after the auto refresh cycles are complete, the sdram is ready for mode register programming. because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. mode register definition the mode register is used to define the specific mode of operation of the sdram. this definition includes the selection of a burst length, a burst type, a cas latency, an operating mode and a write burst mode, as shown in figure 5, mode register definition diagram, on page 7. the mode register is programmed via the load mode register command and will retain the stored information until it is programmed again or the device loses power. mode register bits m0?m2 specify the burst length, m3 specifies the type of burst (sequential or inter- leaved), m4?m6 specify the cas latency, m7 and m8
4mb, 8mb (x32) sdram dimms 09005aef80948ad4 micron technology, inc., reserves the right to change products or specifications without notice. sd2_4c1_2x32udg_a.fm - rev. a 2/03 en 7 ?2003, micron technology inc. specify the operating mode, m9 specifies the write burst mode, and m10 and m11 are reserved for future use. the mode register must be loaded when all device banks are idle, and the controller must wait the speci- fied time before initiating the subsequent operation. violating either of these requirements will result in unspecified operation. burst length read and write accesses to the sdram are burst ori- ented, with the burst length being programmable, as shown in figure 5, mode register definition diagram. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is avail- able for the sequential type. the full-page burst is used in conjunction with the burst terminate com- mand to generate arbitrary burst lengths. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached, as shown in table 7, burst definition table, on page8. the block is uniquely selected by a1?a7 when the burst length is set to two; by a2?a7 when the burst length is set to four; and by a3?a7 when the burst length is set to eight. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. full-page bursts wrap within the page if the boundary is reached, as shown in table 7, burst defini- tion table, on page 8. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is deter- mined by the burst length, the burst type and the start- ing column address, as shown in table 7, burst definition table, on page 8. figure 5: mode register definition diagram 000 001 010 011 100 101 110 111 m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 - 0 - defined - 0 1 burst type sequential interleave cas latency reserved 1 2 3 reserved reserved reserved reserved 000 001 010 011 100 101 110 111 burst length m0 burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m1 m2 m3 m4 m5 m6 m6 - m0 m8 m7 op mode a10 ba 10 11 reserved* wb 0 1 write burst mode programmed burst length single location access m9 *should program m11, m10 = 0, 0 to ensure compatibility with future devices.
4mb, 8mb (x32) sdram dimms 09005aef80948ad4 micron technology, inc., reserves the right to change products or specifications without notice. sd2_4c1_2x32udg_a.fm - rev. a 2/03 en 8 ?2003, micron technology inc. note: 1. for a burst length of two, a1?a7 select the block- of-two burst; a0 selects the starting column within the block. 2. for a burst length of four, a2?a7 select the block- of-four burst; a0?a1 select the starting column within the block. 3. for a burst length of eight, a3?a7 select the block- of-eight burst; a0?a2 select the starting column within the block. 4. for a full-page burst, the full row is selected and a0?a7 select the starting column. 5. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 6. for a burst length of one, a0?a7 select the unique column to be accessed, and mode register bit m3 is ignored. cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first piece of output data. the latency can be set to two or three clocks. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available by clock edge n + m . the dqs will start driving as a result of the clock edge one cycle earlier ( n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m . for example, assuming that the clock cycle time is such that all rele- vant access times are met, if a read command is regis- tered at t0 and the latency is programmed to two clocks, the dqs will start driving after t1 and the data will be valid by t2, as shown in figure 6, cas latency diagram. table 8, cas latency table, on page 9, indi- cates the operating frequencies at which each cas latency setting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result. figure 6: cas latency diagram operating mode the normal operating mode is selected by setting m7 and m8 to zero; the other combinations of values for m7 and m8 are reserved for future use and/or test modes. the programmed burst length applies to both read and write bursts. table 7: burst definition table burst length starting column address order of accesses wthin a burst type = sequential type = interleaved 2 a0 00-1 0-1 11-0 1-0 4 a1 a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-4-5-6-7-0-1-2 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full page (256) n = a0-a7 (location 0- 255) cn, cn + 1, cn + 2, cn + 3, cn + 4. . . cn - 1, cn . . . not supported clk dq t2 t1 t3 t0 cas latency = 3 lz d out t oh t command nop read t ac nop t4 nop don?t care undefined clk dq t2 t1 t3 t0 cas latency = 2 lz d out t oh t command nop read t ac nop
4mb, 8mb (x32) sdram dimms 09005aef80948ad4 micron technology, inc., reserves the right to change products or specifications without notice. sd2_4c1_2x32udg_a.fm - rev. a 2/03 en 9 ?2003, micron technology inc. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. write burst mode when m9 = 0, the burst length programmed via m0- m2 applies to both read and write bursts; when m9 = 1, the programmed burst length applies to read bursts, but write accesses are single-location (non- burst) accesses. table 8: cas latency table speed allowable operating clock frequency (mhz) cas latency = 2 cas latency = 3 -8 100 125 -10 66 100
4mb, 8mb (x32) sdram dimms 09005aef80948ad4 micron technology, inc., reserves the right to change products or specifications without notice. sd2_4c1_2x32udg_a.fm - rev. a 2/03 en 10 ?2003, micron technology inc. commands table 9, truth table ? commands and dqmb oper- ation, provides a general reference of available com- mands. for a more detailed description of commands and operations, refer to the 16mb sdram component data sheets. note: 1. cke is high for all commands shown except self refresh. 2. a0?a10 define the op-code written to the mode register. 3. a0?a10 provide row address and ba0 de termine which bank is made active. 4. a0?a7 provide column address; a10 high enables the auto precharge feature (nonpersistent), while a10 low dis- ables the auto precharge feature; ba0 determine which bank is being read from or written to. 5. a10 low: ba0 determine which bank is being precharged. a10 high: both banks are precharged and ba0 is ?don?t care.? 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are ?don?t care? except for cke. 8. activates or deactivates the dq during write (zero-clock delay) and read (two-clock delay). table 9: truth table ? commands and dqmb operation note: 1 name (function) cs# ras# cas# we# dqmb addr dq notes command inhibit (nop) hxxxxxx no operation (nop) l hhhxxx active (select bank and activate row) llhhxbank/ row x3 read (select bank and column, and start read burst) lhlh l/h 8 bank/col x 4 write (select bank and column, and start write burst) lhl l l/h 8 bank/col valid 4 burst terminate lhhlxxactive precharge (deactivate row in bank or banks) llhlxcodex5 auto refresh or self refresh (enter self refresh mode) lllhxxx6, 7 load mode register llllxop- code x 2 write enable/output enable ????l?active8 write inhibit/output high-z ????h?high-z8
4mb, 8mb (x32) sdram dimms 09005aef80948ad4 micron technology, inc., reserves the right to change products or specifications without notice. sd2_4c1_2x32udg_a.fm - rev. a 2/03 en 11 ?2003, micron technology inc. absolute maximum ratings stresses greater than those listed may cause perma- nent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. voltage on v dd supply relative to v ss . . . . . . . . . . . . . . . . . . . . -1v to +4.6v voltage on inputs, nc or i/o pins relative to v ss . . . . . . . . . . . . . . . . . . . . -1v to +4.6v operating temperature t a (ambient) . . . . . . . . . . . . . . . . . . . . . 0 c to +70 c storage temperature (plastic) . . . . . .-55 c to +125 c power dissipation single rank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2w dual rank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4w table 10: dc electrical characteristics and operating conditions (4mb) note: 1; notes appear on page 16; v dd = +3.3v 0.3v parameter/condition sym min max units notes supply voltage v dd 3.0 3.6 v input high voltage: logic 1; all inputs v ih 2.2 v dd + 0.3 v22 input low voltage: logic 0; all inputs v il -0.3 0.8 v 22 input leakage current: any input 0v v in v dd (all other pins not under test = 0v) we#, ras#, cas#, a0-a10, ba0, ck, cke i i 1 -10 10 a 30 s# i i 2 -5 5 a 30 dqmb i i 3 -5 5 a 4, 30 output leakage current: dq disabled; 0v v out v dd dq i oz -10 10 a 4, 30 output levels: output high voltage (i out = -4ma) output low voltage (i out = 4ma) v oh 2.4 ? v v ol ?0.4v table 11: dc electrical characteristics and operating conditions (8mb) note: 1; notes appear on page 16; v dd = +3.3v 0.3v parameter/condition sym min max units notes supply voltage v dd 3.0 3.6 v input high voltage: logic 1; all inputs v ih 2.2 v dd + 0.3 v22 input low voltage: logic 0; all inputs v il -0.3 0.8 v 22 input leakage current: any input 0v v in v dd (all other pins not under test = 0v) we#, ras#, cas#, a0-a10, ba0 i i 1 -20 20 a 30 ck, cke i i 2 -10 10 a 30 s# i i 3 -5 5 a 30 dqmb i i 4 -10 10 a 4, 30 output leakage current: dq disabled; 0v v out v dd dq i oz -20 20 a 4, 30 output levels: output high voltage (i out = -4ma) output low voltage (i out = 4ma) v oh 2.4 ? v v ol ?0.4v
4mb, 8mb (x32) sdram dimms 09005aef80948ad4 micron technology, inc., reserves the right to change products or specifications without notice. sd2_4c1_2x32udg_a.fm - rev. a 2/03 en 12 ?2003, micron technology inc. ta bl e 1 2 : i dd specifications and conditions (4mb) dram components only notes: 1, 5 , 6 , 11, 13; notes appear on page 16; v dd = v dd q = +3.3v 0.3v max parameter/condition symbol -8 -10 units notes operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd 1 270 260 ma 3, 18, 19, 27 standby current: power-down mode; all device device banks idle; cke = low i dd 2 44ma 27 standby current: active mode; cke = high; cs# = high; all device banks active after t rcd met; no accesses in progress i dd 3 70 60 ma 3, 12, 19, 27 operating current: burst mode; continuous burst; read or write; all device banks active i dd 4 200 160 ma 3, 18, 19, 27 auto refresh current: t rc = 15.625 s; cas latency = 3; cs# = high; cke = high; t ck = 15 n s (10 n s for -8) i dd 5 70 60 ma 3, 12, 18, 19, 27 self refresh current: cke 0.2v i dd 6 22ma 4 ta bl e 1 3 : i dd specifications and conditions (8mb) dram components only notes: 1, 5, 6 , 11, 13; notes appear on page 16; v dd = v dd q = +3.3v 0.3v max parameter/condition symbol -8 -10 units notes operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd 1 a 274 264 ma 3, 18, 19, 27 standby current: power-down mode; all device device banks idle; cke = low i dd 2 b 88ma 27 standby current: active mode; cke = high; cs# = high; all device banks active after t rcd met; no accesses in progress i dd 3 a 74 64 ma 3, 12, 19, 27 operating current: burst mode; continuous burst; read or write; all device banks active i dd 4 a 204 164 ma 3, 18, 19, 27 auto refresh current: t rc = 15.625 s; cas latency = 3; cs# = high; cke = high; t ck = 15 n s (10 n s for -8) i dd 5 b 140 120 ma 3, 12, 18, 19, 27 self refresh current: cke 0.2v i dd 6 b 44ma 4 note: a - value calculated as one module rank in this operating condition, and all other module ranks in power-down mode. b - value calculated reflects all module ranks in this operating condition.
4mb, 8mb (x32) sdram dimms 09005aef80948ad4 micron technology, inc., reserves the right to change products or specifications without notice. sd2_4c1_2x32udg_a.fm - rev. a 2/03 en 13 ?2003, micron technology inc. table 14: capacitance (4mb) notes: 1 , 2 ; t his parameter is sampled; notes appear on page 16; v dd = +3.3v; f = 1 mhz parameter symbol min max units input capacitance: a0-a10, ba0, ras#, cas#, we#, cke c i 1 510 pf input capacitance: ck c i 3 11.8 14.8 pf input capacitance: s# c i 4 2.5 5 pf input capacitance: dqmb c i 5 2.5 5 pf input capacitance: scl, sa0-sa2, sda c i 6 ?6 pf input/output capacitance: dq c io 46.5 pf table 15: capacitance (8mb) notes: 1 , 2 ; t his parameter is sampled; notes appear on page 16; v dd = +3.3v; f = 1 mhz parameter symbol min max units input capacitance: a0-a10 , ba0, ras#, cas#, we# c i 1 10 20 pf input capacitance: cke c i 2 510 pf input capacitance: ck c i 3 11.8 14.8 pf input capacitance: s# c i 4 2.5 5 pf input capacitance: dqmb c i 5 510 pf input capacitance: scl, sa0-sa2, sda c i 6 ?6 pf input/output capacitance: dq c io 813 pf
4mb, 8mb (x32) sdram dimms 09005aef80948ad4 micron technology, inc., reserves the right to change products or specifications without notice. sd2_4c1_2x32udg_a.fm - rev. a 2/03 en 14 ?2003, micron technology inc. table 16: sdram component ac electrical characteristics notes: 1?5, 29; notes appear on pa ge 16; sdram component specifications parameter symbol -8 -10 units notes min max min max access time from clk (positive edge) cl = 3 t ac 67.5ns cl = 2 t ac 99ns22 cl = 1 t ac 22 27 ns 22 address hold time t ah 11 ns address setup time t as 23 ns clk high-level width t ch 33.5 ns clk low-level width t cl 33.5 ns clock cycle time cl = 3 t ck 810 ns23 cl = 2 t ck 13 15 ns 22, 23 cl = 1 t ck 25 30 ns 23 cke hold time t ckh 11 ns cke setup time t cks 33 ns cs#, ras#, cas#, we#, dqm hold time t cmh 11 ns cs#, ras#, cas#, we#, dqm setup time t cms 23 ns data-in hold time t dh 11 ns data-in setup time t ds 23 ns data-out high-impedance time cl = 3 t hz 68ns10 cl = 2 t hz 710ns10 cl = 1 t hz 15 15 ns 10 data-out low-impedance time t lz 12 data-out hold time (load) t oh 2.5 2.5 ns active to precharge command period t ras 48 120,000 50 120,000 ns active to active command period t rc 80 80 ns 22 auto refresh period t ref 64 64 ns 9 active to read or write delay t rcd 24 30 ns 22 refresh period (4,096 cycles) t ref 64 64 ns precharge command period t rp 24 30 ns 22 active bank a to active bank b command period t rrd 16 20 ns transition time t t 0.310120 ns 7 write recovery time t wr 1 clk + 2ns 1 clk t ck 24 10 10 ns 25 exit self refresh to active command t xsr 80 90 ns 20
4mb, 8mb (x32) sdram dimms 09005aef80948ad4 micron technology, inc., reserves the right to change products or specifications without notice. sd2_4c1_2x32udg_a.fm - rev. a 2/03 en 15 ?2003, micron technology inc. table 17: ac functional characteristics notes: 5? 9, 11; notes appear on page 16 parameter symbol -8 -10 units notes read/write command to read/write command t ccd 11 t ck 17 cke to clock disable or power-down entry mode t cked 11 t ck 14 cke to clock enable or power-down exit setup mode t ped 11 t ck 14 dqm to input data delay t dqd 00 t ck 17 dqm to data mask during writes t dqm 00 t ck 17 dqm to data high-impedance during reads t dqz 22 t ck 17 write command to input data delay t dwd 00 t ck 17 data-in to activate command cl = 3 t dal 54 t ck 15, 21 cl = 2 t dal 43 t ck 15, 21 cl = 1 t dal 34 t ck 15, 21 data-in to precharge t dpl 21 t ck 16 last data-in to burst stop command t bdl 00 t ck 17 last data-in to new read/write command t cdl 11 t ck 17 last data-in to precharge command t rdl 11 t ck 21, 26 load mode register command to active or refresh command t mrd 22 t ck 11 data-out to high-impedance from precharge command cl = 3 t roh 33 t ck 6 cl = 2 t roh 22 t ck 6 cl = 1 t roh 11 t ck 6
4mb, 8mb (x32) sdram dimms 09005aef80948ad4 micron technology, inc., reserves the right to change products or specifications without notice. sd2_4c1_2x32udg_a.fm - rev. a 2/03 en 16 ?2003, micron technology inc. notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v dd , v dd q = +3.3v; f = 1 mhz; t a = 25c; pin under test biased at 1.4v. 3. i dd is dependent on output loading and cycle rates. specified values are obtained with mini- mum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured (0c t a +70c). 6. an initial pause of 100s is required after power- up, followed by two auto refresh commands, before proper device operation is ensured. (v dd and v dd q must be powered up simultaneously. v ss and v ss q must be at same potential.) the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 7. ac characteristics assume t t = 1ns. 8. in addition to meeting the transition rate specifi- cation, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a mono- tonic manner. 9. outputs measured at 1.5v with equivalent load: 10. t hz defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 11. ac timing and i dd tests have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point. if the input transition time is longer than 1ns, then the timing is referenced at v il (max) and v ih (min) and no longer at the isv crossover point. 12. other input signals are allowed to transition no more than once every two clocks and are other- wise at valid v ih or v il levels. 13. i dd specifications are tested after the device is properly initialized. 14. timing actually specified by t cks; clock(s) speci- fied as a reference only at minimum cycle rate. 15. timing actually specified by t wr plus t rp; clock(s) specified as a reference only at minimum cycle rate. 16. timing actually specified by t wr. 17. required clocks are specified by jedec function- ality and are not dependent on any timing param- eter. 18. the i dd current will increase or decrease propor- tionally according to the amount of frequency alteration for the test condition. 19. address transitions average one transition every two clocks. 20. clk must be toggled a minimum of two times during this period. 21. based on t ck = 100 mhz for -10; t ck = 125 mhz for -8. 22. v ih overshoot: v ih (max) = v dd q + 2v for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. v il under- shoot: v il (min) = -2v for a pulse width 3ns. 23. the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (read, write, includ- ing t wr, and precharge commands). cke may be used to reduce the data rate. 24. auto precharge mode only. the precharge timing budget ( t rp) begins 7.5ns for -10; and 7ns for -8 after the first clock delay, after the last write is executed. may not exceed limit set for precharge mode. 25. precharge mode only. 26. jedec and pc100 specify three clocks. 27. for -8, cl = 3 and t ck = 7.5ns; for -10, cl = 2 and t ck = 10ns. 28. cke is high during refresh command period t rfc (min) else cke is low. the i dd 6 limit is actually a nominal value and does not result in a fail value. 29. refer to device data sheet for timing waveforms. 30. leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. q 50pf
4mb, 8mb (x32) sdram dimms 09005aef80948ad4 micron technology, inc., reserves the right to change products or specifications without notice. sd2_4c1_2x32udg_a.fm - rev. a 2/03 en 17 ?2003, micron technology inc. spd clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (as shown in figure 7, data validity, and figure 8, defini- tion of start and stop). spd start condition all commands are preceded by the start condition, which is a high-to-low transition of sda when scl is high. the spd device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. spd stop condition all communications are terminated by a stop condi- tion, which is a low-to-high transition of sda when scl is high. the stop condition is also used to place the spd device into standby power mode. spd acknowledge acknowledge is a software convention used to indi- cate successful data transfers. the transmitting device, either master or slave, will release the bus after trans- mitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data (as shown in fig- ure 9, acknowledge response from receiver). the spd device will always respond with an acknowledge after recognition of a start condition and its slave address. if both the device and a write oper- ation have been selected, the spd device will respond with an acknowledge after the receipt of each subse- quent eight-bit word. in the read mode the spd device will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowl- edge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will termi- nate further data transmissions and await the stop condition to return to standby power mode. figure 7: data validity figure 8: definition of start and stop figure 9: acknowledge response from receiver scl sda data stable data stable data change scl sda start bit stop bit scl from master data output from transmitter data output from receiver 9 8 acknowledge
4mb, 8mb (x32) sdram dimms 09005aef80948ad4 micron technology, inc., reserves the right to change products or specifications without notice. sd2_4c1_2x32udg_a.fm - rev. a 2/03 en 18 ?2003, micron technology inc. figure 10: spd eeprom table 18: eeprom device select code most significant bit (b7) is sent first select code device type identifier chip enable rw b7 b6 b5 b4 b3 b2 b1 b0 memory area select code (two arrays) 10 10sa2sa1sa0rw protection register select code 01 10sa2sa1sa0rw table 19: eeprom operating modes mode rw bit wc bytes initial sequence current address read 1v ih or v il 1 start, device select, rw = 1 randomaddressread 0v ih or v il 1 start, device select, rw = 0, address 1v ih or v il restart, device select, rw = 1 sequential read 1v ih or v il 1 similar to current or random address read byte write 0v il 1 start, device select, rw = 0 page write 0v il 16 start, device select, rw = 0 scl sda in sda out t low t su:sta t hd:sta t f t high t r t buf t dh t aa t su:sto t su:dat t hd:dat undefined
4mb, 8mb (x32) sdram dimms 09005aef80948ad4 micron technology, inc., reserves the right to change products or specifications without notice. sd2_4c1_2x32udg_a.fm - rev. a 2/03 en 19 ?2003, micron technology inc. note: 1. the spd eeprom write cycle time ( t wrc) is the time from a valid stop condition of a write sequence to the end of the eeprom internal erase/program cycle. during the write cycle, the eeprom bus interface circuit is disabled, sda remains high due to the pull-up resistor, and the eeprom does not respond to its slave address. table 20: serial presence-detect eeprom dc operating conditions all voltages referenced to v ss ; v dd = +3.3v 0.3v parameter/condition symbol min max units notes supply voltage v dd 33.6v input high voltage: logic 1; all inputs v ih v dd x 0.7 v dd + 0.5 v input low voltage: logic 0; all inputs v il -1 v dd x 0.3 v output low voltage: i out = 3ma v ol ?0.4v input leakage current: v in = gnd to v dd i li ?10a output leakage current: v out = gnd to v dd i lo ?10a standby current: scl = sda = v dd - 0.3v; all other inputs = v dd or v ss i sb ?30a power supply current: scl clock frequency = 100 khz i dd ?2ma table 21: serial presence-detect eeprom ac electrical characteristics all voltages referenced to v ss ; v dd = +3.3v 0.3v parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.3 3.5 s time the bus must be free before a new transition can start t buf 4.7 s data-out hold time t dh 300 ns sda and scl fall time t f 300 ns data-in hold time t hd:dat 0s start condition hold time t hd:sta 4s clock high period t high 4s noise suppression time constant at scl, sda inputs t i 100 ns clock low period t low 4.7 s sda and scl rise time t r 1s scl clock frequency t scl 100 khz data-in setup time t su:dat 250 ns start condition setup time t su:sta 4.7 s stop condition setup time t su:sto 4.7 s write cycle time t wrc 10 ms 1
4mb, 8mb (x32) sdram dimms 09005aef80948ad4 micron technology, inc., reserves the right to change products or specifications without notice. sd2_4c1_2x32udg_a.fm - rev. a 2/03 en 20 ?2003, micron technology inc. table 22: serial presence-detect matrix ?1?/?0?: serial data, ?driven to high?/?driven to low? byte description entry (version) mt2lsdt132u mt4lsdt232ud 0 number of bytes used by micron 128 80 80 1 total number of spd memory bytes 256 08 08 2 memory type sdram 04 04 3 number of row addresses 11 0b 0b 4 number of column addresses 808 08 5 number of module ranks 1or 2 01 02 6 module data width 32 20 20 7 module data width (continued) 000 00 8 module voltage interface levels lvttl 01 01 9 sdram cycle time, t ck (cas latency = 3) 10ns (-10) 8ns (-8) a0 80 a0 80 10 sdram access from clock, t ac (cas latency = 3) 7.5ns (-10) 6ns (-8) 75 60 75 60 11 module configuration type none 00 00 12 refresh rate/type 15.62s / self 80 80 13 sdram width (primary sdram) 16 16 16 14 error-checking sdram data width 000 00 15 minimum clock delay, t ccd 1 t ck 01 01 16 burst lengths supported 1, 2, 4, 8, page 8f 8f 17 number of banks on sdram device 202 02 18 cas latencies supported 1, 2, 3 07 07 19 cs latency 001 01 20 we latency 001 01 21 sdram module attributes unbuffered 00 00 22 sdram device attributes: general attributes 0e 0e 23 sdram cycle time, t ck (cas latency = 2) 15ns (-10) 10ns (-8) f0 a0 f0 a0 24 sdram access from clock, t ac, (cas latency = 2) 9ns 90 90 25 sdram cycle time, t ck (cas latency = 1) 30ns (-10) 25ns (-8) 78 64 78 64 26 sdram access from clock, t ac, (cas latency = 1) 27ns (-10) 22ns (-8) 6c 58 6c 58 27 minimum row precharge time, t rp 30ns (-10) 20ns (-8) 1e 14 1e 14 28 minimum row active to row active, t rrd 20ns 14 14 29 minimum ras# to cas# delay, t rcd 30ns (-10) 20ns (-8) 1e 14 1e 14 30 minimum ras# pulse width, t ras 60ns (-10) 50ns (-8) 3c 32 3c 32 31 module rank density 4mb 01 01 32 command/address setup, t as 3ns (-10) 2ns (-8) 30 20 30 20 33 command/address hold, t ah 1ns 10 10 34 data signal input setup, t ds 3ns (-10) 2ns (-8) 30 20 30 20 35 data signal input hold, t dh 1ns 10 10
4mb, 8mb (x32) sdram dimms 09005aef80948ad4 micron technology, inc., reserves the right to change products or specifications without notice. sd2_4c1_2x32udg_a.fm - rev. a 2/03 en 21 ?2003, micron technology inc. 36-61 reserved bytes ?00 00 62 spd revision rev. 2 02 02 63 checksum for bytes 0-62 (-10) (-8) 7e c9 7f ca 64 manufacturer's jedec id code micron 2c 65-71 manufacturer's jedec id code (cont.) ff 72 manufacturing location 1-11 01-0b 73-90 module part number (ascii) variable data 91 pcb identification code 1-9 01-09 92 identification code (cont.) 000 93 year of manufacture in bcd variable data 94 week of manufacture in bcd variable data 95-98 module serial number variable data 99-127 manufacturer-specific data (rsvd) ? table 22: serial presence-detect matrix ?1?/?0?: serial data, ?driven to high?/?driven to low? byte description entry (version) mt2lsdt132u mt4lsdt232ud
4mb, 8mb (x32) sdram dimms 09005aef80948ad4 micron technology, inc., reserves the right to change products or specifications without notice. sd2_4c1_2x32udg_a.fm - rev. a 2/03 en 22 ?2003, micron technology inc. figure 11: 100-pin dimm dimensions (4mb) note: all dimensions in inches (millimeters) or typical where noted. 0.700 (17.78) typ 0.118 (3.00) (2x) 0.118 (3.00) typ 0.079 (2.00) r (2x) pin 1 0.250 (6.35) typ 0.050 (1.27) typ 0.118 (3.00) typ 0.039 (1.00) typ 0.039 (1.00) r(2x) pin 50 2.850 (72.39) 0.125 (3.18) max 0.054 (1.37) 0.046 (1.17) 1.005 (25.53) 0.995 (25.27) 3.557 (90.34) 3.545 (90.04) 0.128 (3.25) 0.118 (3.00) (2x) pin 100 pin 51 no components this side of module u1 u2 u5 front view back view max min
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.m icron.com, customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trademarks and/or service marks of micron technology, inc. 4mb, 8mb (x32) sdram dimms 09005aef80948ad4 ?2003, micron technology inc. sd2_4c1_2x32udg_a.fm - rev. a 2/03 en 23 figure 12: 100-pin dimm dimensions (mt4lsdt232ud) note: all dimensions in inches (millimeters) or typical where noted. data sheet designation released (no mark): this data sheet contains mini- mum and maximum limits specified over the complete power supply and temperature range for production devices. although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 0.700 (17.78) typ 0.118 (3.00) (2x) 0.118 (3.00) typ 0.079 (2.00) r (2x) pin 1 0.250 (6.35) typ 0.050 (1.27) typ 0.118 (3.00) typ 0.039 (1.00) typ 0.039 (1.00) r(2x) pin 50 2.850 (72.39) 0.157 (4.00) max 0.054 (1.37) 0.046 (1.17) 1.005 (25.53) 0.995 (25.27) 3.557 (90.34) 3.545 (90.04) 0.128 (3.25) 0.118 (3.00) (2x) front view back view pin 100 pin 51 u1 u2 u5 u3 u4 max min

▲Up To Search▲

Price & Availability of MT4LSDT232UDG-8XX

	To Download MT4LSDT232UDG-8XX Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .